Abstract:

A two-step encoding technique that was described in this article is utilised in this article to encode the 12 quasi-cyclic (QC)- low-density parity-check (LDPC) (QC-LDPC) codes that are required by the IEEE 802.11n/ac/ax standards. This strategy was presented in this article. These codes must be used in order to comply with the requirements of the IEEE 802.11n/ac/ax standards. The strategy that has been suggested addresses the collection as a whole rather than focusing on individually addressing each code that is included inside the collection. In the proposed methodology, the operation of multiplication is carried out by using inverse matrices. The new way of encoding makes the procedures of multiplying and dividing numbers quite a bit simpler and more streamlined. It makes it possible to design completely parallel architectures that can decode in a single clock cycle, or even faster with pipelined implementations, for any of the available encoding formats. This is made possible thanks to the fact that it makes it possible to design completely parallel architectures. These architectures may be created for any of the supported encoding formats. While this is going on, we will propose a VLSI encoding architecture that makes use of trees of XOR gates. CSs may be extracted using the recommended technique by capitalising on the structure and characteristics of the related matrices. This is accomplished via the use of common subexpression sharing mechanisms (CSST). These types of expressions are a direct result of the similarities that exist between the original matrices and their inverses, both of which are covered in further detail in the aforementioned article. In this article, we provide innovative methodologies for the extraction of subexpressions that simultaneously target certain codes. Throughputs of up to 1.62 Tbps are attainable by integrating single-clock hardware encoders manufactured using the method described into technologies operating at 1 GHz and requiring a minimum of 125 or 107 KGates, respectively, respectively. These technologies have a 90-nm and 45-nm technology node size

Description:

The terms "common subexpression" (CS), "complexity reduction," "encoding complexity," "lowdensity parity-check" (LDPC) encoding," "matrix inversion"; "multi-Gbps throughput rate;" "quasi-cyclic" (QC) LDPC; and "very large scale integration" (VLSI) architecture are all terms associated with these concepts